Phase change memory (also known as phase change random access memory, PCRAM), emerging along with the development of nano processing technology, is a new generation of non-volatile semiconductor memory, compatible with complementary metal-oxide semiconductor (CMOS) integrated circuit. As the device feature size is scaling down to nanometer range and continuing to decrease, the memory characteristics of PCRAM based on reversible phase change resistor exhibit greater performance (eg. low power consumption and high speed) at several nanometer scale and are better in the overall performance than currently commercialized flash memory technology. Therefore it is universally regarded as a significant breakthrough of memory technology apart from flash in the industry, enjoying a high competitive position and extensive commercial value in future memory market. As a result, major semiconductor memory manufacturers in the world have taken PCRAM as an alternative technology of flash and dynamic random access memory (DRAM) after 45 nm node and as an emphasis in research and development since 2002 as well.
Among various kinds of mature memories, metal-oxide-semiconductor field-effect transistor (MOSFET) is widely used as a selector switch device. A high transient current (of about 0.5-2 mA/cell) is required for PCRAM to execute RESET operation. If MOSFET is chosen as a selector switch, the trench width must be increased to meet the requirements of high current and the cell area is necessary to be increased as well. Some international corporations, including Renesas, adopt a structure of MOSFET+phase change resistor, wherein the cell area is in the range of 25 to 45 F2 (wherein F is the dimension of the minimum half-period of active area at a technology node, and, taking the design rule of 45 nm logic circuit as an example, the minimum dimension of both active area and oxidation isolation region are 70 nm, so F is equal to 70 nm and F2 is equal to 4900 nm2). The larger the cell area, the less competitive the technology. Currently, the cell area of DRAM and flash is substantially in the range of 6 to 12 F2; therefore, if MOSFET is used as the selector switch, it's impossible to take part in the competition of high-density large-capacity memories and can only be applied to certain special fields.
In order to improve the current driving capability of the selector switch device and maintain the memory cell area, bipolar device is the optimum choice; therefore, the development as well as the fabrication of bipolar driving device is the key to the industrialization of high-density large-capacity PCRAM chip.
Samsung has developed patent technologies of diode array fabrication utilizing selective silicon epitaxy as the key technology, wherein the cell area is about 5.8 F2. However, due to the adoption of selective epitaxy, which has a high requirement of process flow and high fabrication cost as a result and by which the diodes are fabricated after the fabrication of CMOS transistors, the thermal process for selective epitaxial single crystal silicon is able to incur performance drift of sensitive 45 nm CMOS transistor devices such that the yield of 45 nm CMOS logic circuits is decreased and the whole set of process is not suitable to be applied to embedded phase change random access memory at 45 nm. Zhang Ting etc. from Shanghai Institute of Mircrosystem and Information Technology under Chinese Academy of Sciences disclosed a structure of dual shallow trench isolated diode array and fabrication process thereof (CN Patent, Manufacturing Method of Bipolar Transistor Array Isolated by Double Shallow Slots, Application No.: 200810041516.5), wherein current semiconductor manufacturing process is adopted to form heavily-doped low resistance word lines by deep trench and sidewall diffusion doping and then to form bipolar transistor by ion implantation and lithography, and wherein two methods as follow are adopted to form heavily-doped low resistance word lines: 1. upon the deep trench etch, undoped or P type doped oxide is deposited on the trench bottom before N type heavily-doped arsenic silicon glass is deposited thereon and etched back to certain depth, and then thermal diffusion process is carried out; 2. when the deep trench is etched to half of the depth, arsenic silicon glass is deposited thereon and etched back to certain depth, and then thermal diffusion process is carried out before the removal of arsenic silicon glass and subsequent deep trench etch to a specified depth.
The challenge of fabricating high-density diode array at nanometer scale is to effectively reduce the crosstalk current between adjacent word lines and bit lines. Due to the decrease of size, the distance between adjacent word lines decreases accordingly and the leakage current through P type substrate between word lines increases; when a large current pulse flows through a selected word line, the non-selected word lines adjacent to it will be disturbed by the switching noise to misoperate, and the nonuniformity of both the deep trench depth and the bottom depth of word line buried layer will increase the possibility of signal interference between adjacent word lines. Meanwhile, due to the decrease of the distance between bit lines and the depth of shallow trenches, large crosstalk current between adjacent bit lines will cause misoperation. Based on this, the present invention provides a method of fabricating dual trench isolated epitaxial diode array, wherein, by optimization of the method, the crosstalk current between adjacent bit lines and word lines can be effectively prevented, and therefore make it suitable to be applied to diode-driven, high-density large-capacity memories, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory.